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The I C transmitter is double buffered through the transmit buffer and transmit shift register as shown
in I2Cn_CMD. This will prevent the I C module from transmitting the data in the buffer and shift register,
Like the transmitter, the I C receiver is double buffered. The receiver uses the receive buffer and receive
the START bit in I2Cn_CMD. The command schedules a START condition, and makes the I C module
The I C-bus is considered busy whenever another device on the bus transmits a START condition. Until
immediately, but if the buffer is empty, the master holds the I C-bus while waiting for software to write
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15.3.6 Buffers
15.3.6.1 Transmit Buffer and Shift Register
2
in Figure 15.1 (p. 145) . A byte is loaded into the transmit buffer by writing to I2Cn_TXDATA. When
the transmit shift register is empty and ready for new data, a byte from the transmit buffer is loaded into
the shift register if available. The byte is then kept in the shift register until it is transmitted. When a byte
has been transmitted, a new byte is loaded into the shift register if available. If the transmit buffer is
empty, the shift register remains empty, and the TXC flag in I2Cn_STATUS and the TXC interrupt flags
in I2Cn_IF are set, signaling that the shift register transmitter is out of data. TXC is cleared when new
data becomes available, but the TXC interrupt flag must be cleared by software.
Whenever a byte is loaded from the transmit buffer to the transmit shift register, the TXBL flag in
I2Cn_STATUS and the TXBL interrupt flag in I2Cn_IF are set, indicating that there is room in the buffer
for more data. TXBL is cleared automatically when data is written to the buffer.
If a write is attempted to the transmit buffer while it is not empty, the TXOF interrupt flag in I2Cn_IF is set,
indicating the overflow. The data already in the buffer is in that case preserved, and no data is written.
The transmit buffer, including the transmit shift register can be cleared by setting command bit CLEARTX
2
and will make them available for new data. Any byte currently being transmitted will not be aborted.
Transmission of this byte will be completed.
15.3.6.2 Receive Buffer and Shift Register
2
shift register as shown in Figure 15.1 (p. 145) . When a byte has been fully received by the receive
shift register, it is loaded into the receive buffer if there is room for it. Else, the byte waits in the shift
register until space is available in the buffer.
When a byte becomes available in the receive buffer, the RXDATAV in I2Cn_STATUS and RXDATAV
interrupt flag in I2Cn_IF are set, and the data can be fetched from the buffer using I2Cn_RXDATA.
Reading from this register will pull a byte out of the buffer, making room for a new byte and clearing
RXDATAV in I2Cn_STATUS and RXDATAV in I2Cn_IF in the process.
If a read from the receive buffer is attempted through I2Cn_RXDATA while the buffer is empty, the RXUF
interrupt flag in I2Cn_IF is set, and the data read from the buffer is undefined.
I2Cn_RXDATAP can be used to read data from the receive buffer without removing it from the buffer.
The RXUF interrupt flag in I2Cn_IF will never be set as a result of reading from I2Cn_RXDATAP, but
the data read through I2Cn_RXDATAP when the receive buffer is empty is still undefined.
15.3.7 Master Operation
A bus transaction is initiated by transmitting a START condition (S) on the bus. This is done by setting
2
generate a start condition whenever the bus becomes free.
2
a STOP condition is detected, the bus is owned by the master issuing the START condition. The bus is
considered free when a STOP condition is transmitted on the bus. After a STOP is detected, all masters
that have data to transmit send a START condition and begin transmitting data. Arbitration ensures
collisions are avoided.
When the START condition has been transmitted, the master must transmit a slave address (ADDR)
with an R/W bit on the bus. If this address is available in the transmit buffer, the master transmits it
2
the address to the transmit buffer.
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